The recent three-dimensional packaging technology of semiconductors in production processes of semiconductor devices employ semiconductor substrates having through-silicon via (TSV) structures. Polishing of semiconductor substrates having through-silicon via structures may be challenging because a material for a through-silicon via and silicone—a semiconductor material—are polished simultaneously and thus a feature of polishing, particularly the polishing speed or the surface accuracy after polishing, differs between the materials for through-silicon vias and silicon.
The method of polishing semiconductor substrates having through-silicon via structures has been conventionally studied. For example, Patent document 1 discloses a polishing composition containing an oxidizing agent which is hydrogen peroxide and a complexing agent. Patent document 1 discloses that using the polishing composition, contamination of silicon wafers with copper was reduced.
Meanwhile Patent document 2 discloses that using the polishing composition disclosed in Patent document 2, a silicon configuration and a conductive material configuration formed of copper can be polished at the same polishing speed of 6000 Å/min. It is disclosed that the polishing composition disclosed in Patent document 2 contains an organic alkaline compound and an oxidizing agent which is sodium chlorite or potassium bromate and that the organic alkaline compound is an amine such as ethylenediamine, diethylenetriamine, triethylenetetramine, N-(2-hydroxyethyl)ethylenediamine and 1,2-diaminopropane.
The polishing composition disclosed in Patent document 2 is formulated in order to polish, as described above, the silicon configuration and the conductive material configuration formed of copper at a similar polishing speed.